As is known, digital signals are conventionally transmitted through a variety of media such as, for example, radio communication links. Such digital signals are transmitted at a rate referred to as the data rate or the clock signal frequency. To decode these signals upon reception, it is necessary to generate a recovered clock signal having a frequency and phase equal to the original clock signal. Once generated, the recovered clock signal is then used to sample the incoming signal at the appropriate times to recover the incoming data information.
Various clock recovery techniques are known in the prior art. One traditional method of clock recovery in a binary environment used the limited version of the data to define the location of the "data edges". The polarity of the receive clock at this data edge defines whether the edge is "early" or "late" with respect to the recovered clock. The appropriate actions may then be taken to correct the phase of the recovered clock.
To more efficiently transmit data, it is common to combine two or more binary data streams to form a multilevel digital signal. To further reduce spectrum consumption, such a multilevel digital signal is usually filtered to remove the excess high-frequency components. This band-limiting process results in a composite multi-level signal whose data edges have smooth or rounded transitions between logic levels.
Such a multilevel signal 100, as in the prior art, is shown in FIG. 1. Referring now to FIG. 1, the signal 100 includes a first +3 level designated 121, a second +1 level designated 123, a third -1 level designated 125, and a fourth -3 level designated 127.
It will be appreciated that if a traditional binary-waveform clock-recovery method with a single threshold is used with the 4-level signal of FIG. 1, the data edges not passing through the limiter's single threshold are not recovered. The 4-level data edges that pass through this traditional single threshold may or may not cross at the true data edge, namely the middle of the transition between the initial logical level and the final logical level in the 4-level data stream.
One prior art technique for extracting a clock signal from a band-limited multi-level signal such as that of FIG. 1 is disclosed in Joseph P. Predina et al., U.S. Pat. No. 4,339,823, entitled "Phase Corrected Clock Signal Recovery Circuit," issued on Jul. 13, 1982, and assigned to Motorola, Inc. (hereinafter "Predina"), which patent is hereby incorporated by reference. As disclosed in Predina, this method uses a transition marker generator which generates a pulse when any threshold is crossed. Referring to FIG. 1, this produces a cluster of transition pulses (corresponding to Predina's FIG. 5A "transition marker group") in the region 141 which is wider than the data edge region 107 produced by a standard limiter. Each transition marker group is followed by an eye interval 143, corresponding to Predina's FIG. 5A elements 100', 110', 120'.
Referring still to Predina, it will be appreciated that his method locks the recovered clock to the transition marker group as follows: The transition marker group is sent to a phase error detector and an electronically-tuned bandpass filter (hereinafter "ETBPF"). The ETBPF then extracts the fundamental harmonic of the clock, which a phase lock loop (PLL) locks to, thereby producing a recovered clock. The phase error detector then compares the transition marker group to the phase of the recovered clock and then adjusts the phase shift of the ETBPF accordingly which, in turn, adjusts the phase of the recovered clock. By this process, the recovered clock's falling edge tries to remain centered with respect to the transition marker group. The problem with this method is, of course, that the transition marker group itself occupies a random position within the region 141, resulting in clocking errors.
As a result, there is a need for an improved method for clock recovery from a multi-level signal.